The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advancements to be realized, similar developments in IC processing and manufacturing are needed.
For example, when forming source/drain (S/D) contacts for small-scaled transistors, such as field effect transistors (FET) having fin-like channel (so-called “FinFETs”), it is sometimes desired to dope S/D features with additional dopants to increase the performance of the devices. Since n-type and p-type FETs may require different dopants, a doping mask is therefore created to mask either the p-type devices or the n-type devices for the doping process. However, patterning and removing this doping mask has become a challenge for the increasingly smaller devices. For example, when creating this doping mask for p-type devices, some over-etching may be required to ensure that there is no mask residue on the p-type S/D features. Such over-etching often leads to reduced mask area for the n-type devices. Consequently, doping the p-type S/D features may inadvertently introduce p-type dopants to the n-type devices.
Some improvements in the S/D contact formation are desired.